Introduction

The 2114 RAM chips used as standard in the Acorn Atom are pretty inefficient, certainly by modern standards. Even the more thrifty 'L' type still draws 35 mA per chip (840 mA for the full complement of 24).

Surprisingly, however, there is a CMOS flavour : the Solid State Scientific SCM21C14. Among other things, this has an auto power down mode. When used in the Atom, this means that only one pair of 12 is drawing full power at any one time, while the others are napping (except for VDG accesses). All in all, a full complement of 21C14 chips draws only (roughly) 120 mA. Quite a saving in terms of power consumption and heat dissipation.

An SCM21C14-3

Of course, there are alternatives to using 2114 chips in the first place, e.g. modern, larger capacity SRAM chips on 'plug-in' boards. But these are big, and may require flying wires, depending on the setup. When the standard amount of memory in the Atom suffices, simply plugging in 21C14s is the easier way.

The snag

Unfortunately, the 21C14 has a special timing requirement. It needs a little bit of time to 'wake up' from a power down, which, in practice, means that nWE may not follow nCE too closely (e.g., for the '-3' speed grade (150 ns access time), the minimum distance is 50 ns).

This does not pose a problem for RAM exclusively accessed by the CPU (ICs 10 through 19, 51 and 52, where nCE to nWE is roughly 450 ns), but it does for the 'video RAM', which is accessed by both the CPU and the VDG (ICs 32 through 43, where, due to the 'shared' construction, nCE to nWE is only roughly 6 ns).

The solution

Solution 1 : don't use 21C14s as video RAM. This is perfectly acceptable, but does not take full advantage of the potential savings.

Solution 2 : sufficiently delay the leading edge of nWE to video RAM. This can be achieved relatively easily by moving IC27 (81LS95) to a little patch PCB that leaves most of the existing socket-to-IC connections intact, but makes the following alternative connections among pins 14 through 18 (SKxx are the socket pins, CHxx are the 81LS95 pins) :

This uses the two previously unused buffers in IC27 to create an extra delay in the leading edge of NWDS, making the nCE to nWE delay roughly 46 ns. This is okay for the 21C14-1 (40 ns required) and 21C14-2 (45 ns), but for the 21C14-3 (50 ns), the timing is still marginal. It is therefore recommended to replace IC30 (74LS138) as well, with either a 74F138 or a 74S138 (gaining an extra 12 to 16 ns due to speeding up nCE).

Resulting in (for example) the following IC27 replacement :

IC 27 fixup (front) IC 27 fixup (back)

Signing off

Feel free to use this information in any way you please, as long as you don't make any money with it.

Research and this text by John Kortink.